1. Field of Use
The present invention relates to a transparent high speed buffer memory or "cache" for data processing systems.
2. Description of Prior Art
It is known in data processing systems that in order to increase performance and to use the resources most efficiently, it is required that the operative speed at which the memory is capable of providing information to the central processing unit or, in case of multiprocessor systems, the processors, be greater than the operating speed of the central unit or the processors.
Usually the working memory is a "bottleneck" which slows down the working speed and decreases the system performance. Several arrangement have been proposed to remove this drawback.
One arrangement provides a working memory operating with multiple central processing units or several processors wherein the memory is divided into banks, blocks or with an interleaved structure. By dividing the memory in banks, several, independently addressable memories are obtained which may service simultaneous read write operations requested by different processors, provided these operations address different banks.
With an interleaved structure it is possible to simultaneously read or write in a plurality of memory locations having contiguous addresses (for instance even or odd) so that at each read/write request at a given address, the read/write operation of an information at a contiguous address is performed.
By providing suitable interface buffer registers between the central unit and the memory it is possible, in case the plurality of information handled by the central unit has sequential addresses, to halve the number of memory accesses. With the advent of data processing systems having 32 bits word this approach is expensive, because it requires a parallel readout of 64 bits.
A different arrangement, frequently used in computers of relatively high power, provides associative memories or "caches" dedicated to several processors which form the system. Such memories store a copy of information blocks recorded in the working memory, as well as the corresponding address. If a processor issues a memory read command for reading at a predetermined address, and this address is found to be present in the cache, the requested information is read out from cache and the working memory is not involved.
If the requested information is not in the cache, the requested information is read out from memory and a cache loading process is started. The requested information is then loaded into the cache, together with a block of information items having addresses contiguous to the address of the requested information.
The structure of such caches is complex and expensive, in that they require logical control circuits which supervise the updating of the cache contents when required, both for a better utilization of the information stored therein, and also to assume that the information stored in cache is the same information that is stored in working memory. This is despite the fact that another system processor may update working memory.
These limitations are overcome by the cache memory of the present invention, which is simple, compact and suitable for embodiment in an integrated circuit.
While in the prior art caches, the loading criterion is the loading of an information block when the requested information is not found in the cache, the criterion used by the cache structure which is the object of the present invention is that for each information requested to the memory, be it present in or missing from the cache, the cache is loaded with the information stored in main memory at the next following address.
In other words the criterion of "prevailing sequentiality" is exploited, wherein instructions and program data are stored in working memory to advance the reading of information in the reasonable prediction that, if information is requested which is stored at a given address, the information stored at the next following address is likely to be requested and is therefore made available without the delays intrinsic to a read memory operation.
This criterion is exploited in U.S. Pat. No. 4,620,277 to provide an early memory addressing of a control store dedicated to a single CPU in a multiple CPU environment.
The scope of the present invention is to provide a cache memory which can be used with a memory shared by multiple CPU and used for storing both instructions and data. The cache memory provides an early memory addressing which exploits at best the "prevailing sequentiality" criterion.